Operational Transconductance Amplifier Research Articles

1 V Tunable High-Quality Universal Filter Using Multiple-Input Operational Transconductance Amplifiers

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of −43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology.

Design of Low Noise Low Power Instrumentation Amplifier for Biomedical Applications

Advancements in integrated circuit (IC) technology and circuit design are enabling devices to replace complex biological applications. Despite this progress, achieving necessary functionality at low power levels is crucial for fully integrated systems. Biomedical devices like pacemakers, which require ongoing battery charging, operate at nanowatt power levels over several years. To ensure long-term pacemaker survival, an Analog Front End (AFE) with low to moderate power consumption and high precision is essential. The front-end Instrumentation Amplifier (INA) is vital for signal acquisition, significantly improving the effectiveness of ECG signal collection systems.The primary aim of this research is to develop an integrated ECG instrumentation amplifier (INA) that can deliver top-notch performance while keeping noise and power consumption to a minimum. This amplifier will enable seamless monitoring of the ECG signal without interruptions. Using an AC connected Common Mode Feedback system [1]. in conjunction with an Operational Trans-conductance Amplifier (OTA) that uses a Chopper stabilization technique, the study's band pass filtering response within the ECG signal frequency range of 0-100Hz is obtained as anticipated. CMOS 45 nm technology is used throughout the entire process using Mentor Graphics EDA Tools

Utilizing layout effects for analog logic locking

AbstractWhile numerous obfuscation techniques are available for securing digital assets in the digital domain, there has been a notable lack of focus on protecting intellectual property (IP) in the analog domain. This is primarily due to the relatively smaller footprint of analog components within an integrated circuit (IC), with the majority of the surface dedicated to digital elements. However, despite their smaller nature, analog components are highly valuable IP and warrant effective protection. In this paper, we present a groundbreaking method for safeguarding analog IP by harnessing layout-based effects that are typically considered undesirable in IC design. Specifically, we exploit the impact of length of oxide diffusion and well proximity effect on transistors to fine-tune critical parameters such as transconductance ($$g_{m}$$ g m ) and threshold voltage ($$V_{th}$$ V th ). These parameters remain concealed behind key inputs, akin to the logic locking approach employed in digital ICs. Our research explores the application of layout-based effects in two commercial CMOS technologies, namely a 28 nm and a 65 nm node. To demonstrate the efficacy of our proposed technique, we implement it for locking an operational transconductance amplifier. Extensive simulations are performed, evaluating the obfuscation strength by applying a large number of key sets (over 50,000 and 300,000). The results exhibit a significant degradation in performance metrics, such as open-loop gain (up to 130 dB), phase margin (up to 50$$^\circ $$ ∘ ), 3 dB bandwidth (approximately 2.5 MHz), and power consumption (around 1 mW) when incorrect keys are employed. Our findings highlight the advantages of our approach as well as the associated overhead.

A 0.3 V OTA with Enhanced CMRR and High Robustness to PVT Variations

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved.

0.5 V Multiple-Input Fully Differential Operational Transconductance Amplifier and Its Application to a Fifth-Order Chebyshev Low-Pass Filter for Bio-Signal Processing.

This paper presents a multiple-input fully differential operational transconductance amplifier (MI-FD OTA) with very low power consumption. To obtain a differential MOS pair with minimum supply voltage and minimum power consumption, the multiple-input bulk-driven MOS transistor operating in the subthreshold region is used. To show the advantage of the MI-FD OTA, a fifth-order Chebyshev filter was used to realize a low-pass filter capable of operating with a supply voltage of 0.5 V and consuming 60 nW at a nominal setup current of 3 nA. The proposed filter uses five MI-FD OTAs and five capacitors. The total harmonic distortion (THD) was 0.97% for a rail-to-rail sinusoidal input signal. The MI-FD OTA and the filter application were designed and simulated in the Cadence environment using a 0.18 µm CMOS process from TSMC. The robustness of the design was confirmed by Monte Carlo analysis and process, voltage, and temperature corner analysis.

Nature inspired algorithm based design of near ideal fractional order low pass Chebyshev filters and their realization using OTAs and CCII

Fractional order filters offer greater freedom of design and a precise control over stopband attenuation in electronic circuits and systems. This paper presents the design of a fractional order low pass Chebyshev filter (FOLCF) that achieves near-ideal response characteristics. The methodology introduced utilizes metaheuristic optimization methods, including particle swarm optimization, firefly algorithm, and grey wolf optimization. These techniques are employed to precisely adjust the filter coefficients for the orders (1+α), (2+α), and (3+α). The adjustment is carried out by comparing the desired behaviour of the FOLCF with generalized fractional order low pass transfer functions. Throughout these instances, the parameter α is varied within the range of (0, 1). The designed filters are then tested and compared on the basis of various factors. Simulation results demonstrate that the designed filters closely follow the behaviour of an ideal Chebyshev filter with maximum passband and stopband magnitude errors being −31.93 dB and −52.74 dB respectively for (1+α) order filters. These values for (2+α) and (3+α) order FOLCF have been observed to be −30.04 dB and −55.91 dB; −17.72 dB and −49.52 dB respectively. Furthermore, it has been observed that the proposed work outperforms existing state-of-the-art approaches in various aspects, including magnitude error, stopband attenuation, and cut-off frequency. The stability of the designed filters has been verified through stability analysis. Additionally, practical feasibility of the proposed FOLCF is demonstrated through SPICE simulations for α = [0.2,0.5,0.8] using second generation current conveyor (CCII) and operational transconductance amplifier (OTA) based topologies while approximating the constant phase element using fifth order continued fraction expansion. The SPICE implementations closely follow the behaviour of ideal filter with −48.67 dB and −62.8 dB as mean square errors for CCII and OTA circuits respectively, showcasing the proposed filters' superiority and practical applicability in advanced electronic design.

CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters

CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters

A linear cross-coupled gate-driven quasi-floating bulk low-power wide input range transconductor.

High linearity for a wider input voltage range and low-power operation of the operational transconductance amplifier (OTA) are indispensable parameters for health care applications, which require high quality and accurate signal conditioning. However, achieving low-power operation along with high linearity at low supply voltages is challenging for OTA using conventional low-power and linearization techniques. This paper proposes an OTA based on a cross-coupled gate-driven quasi-floating bulk (CGDQFB) MOSFET and source-degenerated linearization techniques, which works at a supply of ±0.5V. The post-layout simulations of the proposed OTA are performed in the 180nm standard CMOS process, which shows a transconductance of 0.321 μS, an output impedance of 331 MΩ, an input impedance of 897 GΩ, a DC gain of 40.54 dB, a gain-bandwidth of 0.145MHz, a total harmonic distortion (THD) of 51.09 dB for an input voltage range of 626.7 mV at a frequency of 100.39Hz, and a power consumption of 0.45 μW. The proposed OTA shows an input common mode range of -0.34 to 0.4V, an output voltage swing of -0.34 to 0.34V, a common mode rejection ratio of 91.08 dB, and a consumption area of 23 965.92 µm2. Furthermore, with 200 Monte Carlo iterations, the proposed OTA shows variability for gain and THD of 0.003 and 0.036, respectively. The proposed CGDQFB OTA is a suitable contender for conditioning bio-signals used in health care applications.

A 23.7‐uW 93.5‐dB SNDR delta‐sigma modulator for healthcare and medical diagnostics

AbstractThis paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply.

1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA.

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter-amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta-sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Abstract The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.

Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design’s novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 [Formula: see text]W. Additionally, notable improvements in noise performance are achieved and found to be [Formula: see text][Formula: see text]nV/[Formula: see text] at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is [Formula: see text] dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition.

Design of carbon allotrope FET-based folded cascode operational transconductance amplifiers (FC-OTA)

ABSTRACT Throughout this study, a high-gain, low-energy folded cascode operational transconductance amplifier (FC-OTA) was modelled utilising HSPICE software. The FC-OTA designs included implementations availing CNFETs, GNRFETs, and mixed involving a combination of CNFETs with CMOS. Comparison with traditional CMOS-based FC-OTAs revealed that CNFET-based FC-OTAs exhibited considerable enhancements, displaying significant escalation in DC amplification, output resistance, average power dissipation, and CMRR. The phase margin in CNT-based FC-OTAs indicated stability. Moreover, CNT-based devices showed substantial rise in direct current amplification over GNRFET-FC-OTAs. The study further explored the operational effectiveness of proposed FC-OTAs by varying parameters such as CNT diameter, CNT pitch, and the number of CNTs, identifying optimal values that significantly enhance the FC-OTA’s performance. Comprehensive parametric and Monte Carlo analyses demonstrated OTA’s resilience to changes in supply voltage, temperature, capacitance, and mismatches. In summary, the folded cascode approach was found to enhance gain and reduce average power in CNFET-based FC-OTAs in comparison to other structural configurations.

A Capacitive-Feedback Amplifier with 0.1% THD and 1.18 μVrms Noise for ECG Recording

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm2. The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mVpp output. The amplifier can provide a noise level of 1.18 μVrms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μVrms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

Design of low‐voltage low‐noise operational transconductance amplifiers for low frequency applications

AbstractLow‐noise and low‐voltage operation is prime requirement of an operational transconductance amplifier for low frequency applications. However, achieving low‐noise operation at low supply voltages is a challenging task in CMOS technology owing to noise‐power and noise‐stability tradeoffs. This article outlines, the design of four differential bias self‐cascode (DBSC) operational transconductance amplifiers (OTAs) working at ±0.7 V. The four design techniques namely gate driven (GD), bulk driven (BD), bulk driven quasi‐floating gate (BDQFG), and gate driven quasi floating bulk (GDQFB) have been applied on DBSC OTAs. The designing aspects and performance parameters of these four OTAs such as gain, gain‐bandwidth, input referred noise (IRN), settling time (ST), common mode rejection ratio (CMRR), total harmonic distortion, input impedance, transconductance, power consumption, area consumption and process/mismatch variations have been fairly compared in this work. These DBSC OTAs have been designed and simulated using a standard 0.18‐μm 6M1P CMOS N‐well process. The results infer GD DBSC OTA shows high CMRR of 125.83 dB. While the BD DBSC OTA consumes very low power of 0.2 μW. The BDQFG DBSC OTA shows low 1% ST of 24.83 μS. The GDQFB DBSC OTA show high transconductance (2.35 mS), high gain (64.97 dB), and low IRN (0.40 μV/√Hz at 10 Hz). The theoretical predictions for these OTAs agree with the post‐layout simulations. The proposed OTAs can be used for designing various analog circuits such as programmable gain amplifiers, variable gain amplifiers, and transimpedance amplifiers for low‐frequency biomedical and health care applications.

On the design of an ultra-low-power ultra-low-voltage inverter-based OTA

In this paper, an inverter-based Operational Transconductance Amplifier (OTA) is introduced. This design is tailored for applications demanding ultra-low power consumption and exceptionally reduced supply voltage. In addition to the utilization of composite transistors and forward-body-biasing, a feedforward path is also employed to enhance the voltage gain. The OTA is simulated in a 65 nm CMOS technology with a supply voltage of 0.3 V. Simulation results show a voltage gain of 42.57 dB and a power consumption of 1.06 nW.

Low power three-stage OTA using reverse nested frequency compensation without nulling resistor

This study introduces a novel reverse nested miller compensated high gain three stage operational transconductance amplifier (OTA) that exhibits lower power consumption and maximum allowable voltage swing. In this context, two amplifiers have been employed. The initial amplifier employs PMOS as the primary amplifying component, with a specified IDD value of 200 A. In the subsequent stages, both the second and third amplifiers are biased to operate at a current level of 2 times IDD. These operations are conducted within a 45 m Cadence Virtuoso environment. The other three-stage amplifier employs PMOS as the primary amplifier, with a bias current (IDD) of 4 μA. In a 90 m Cadence Virtuoso environment, both the second and third stages are biased to operate at a current of 5 times IDD. The primary design criteria introduced in this design approach are gain, phase margin, and power consumption, which are thoroughly stated. The circuits undergo Monte Carlo and corner evaluations, and the findings are deliberated about in the conclusion of the research. In order to attain the greatest allowable voltage swing, these amplifiers are fabricated with VDD values of 500 m and 900 m. The output voltage is set to a constant value of VDD/2.

A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator

This paper presents a 3rd-order discrete-time delta-sigma modulator (DT DSM) with ring-amplifier-based integrators. To fulfill the performance requirement of the switched-capacitor (SC) integrator for the DSM with low power consumption, a dynamic ring amplifier is employed to replace the conventional continuous-time operation transconductance amplifier (OTA) in the integrator. The offset and 1/f noise of the 1st-stage integrator are further suppressed with an auto-zero structure. The quantizer is realized by a 3-bit flash analog-to-digital converter (ADC) to reduce the quantization noise power, while the mismatch in the feedback digital-to-analog converter (DAC) is suppressed by a dynamic weighting averaging (DWA) circuit. The DT DSM prototype is fabricated with a 0.18-μm CMOS process with an active area of 1.39 mm2, achieving 99.3 dB SNDR and 104.3 dB DR with a signal bandwidth of 10 kHz and an oversampling ratio of 128. The power consumption is 963.9 μW under a 3.3V power supply, corresponding to a Schreier figure-of-merit(FoMs) value of 174.5 dB.

Design of a high bandwidth ECG signal low noise amplifier circuit for wearable devices

Nowadays, more than one million people die due to heart problems annually. Detecting the Electrocardiogram curve is an effective way to evaluate heart condition. Compared with large devices in the hospital, wearable devices are showing their advantage in detecting peoples Electrocardiogram whenever and wherever possible. However, in traditional amplifier circuit design, there is less attention to the bandwidth. The noise is negatively correlated with the current while the power consumption is positively correlated with the current, so it is challenging to balance the noise and power. Therefore, a design of a high bandwidth Electrocardiogram signal low noise amplifier circuit for wearable devices is proposed in this paper. The improved circuit is based on a conventional instrumentation amplifier and consists of two stages. The op-amps were replaced with Operational Transconductance Amplifier. The circuit also has a Driven-Right-Leg circuit part, which can tremendously reduce the effect of common-mode noise. The simulation result shows that the circuit has a high bandwidth and stable gain. Meanwhile, the circuit consumes less power and has a low integrated input-referred noise. This study is extremely helpful in expanding the application of wearable Electrocardiogram signal-detecting devices.